Design for testing or design for testability (DFT) generally includes integrated circuit (IC) design techniques that add testability features to a hardware product design. The added features often make it easier to develop and apply manufacturing tests to the designed hardware. Often the purpose of manufacturing tests is to validate that the product hardware contains no design or manufacturing defects that could adversely affect the product's correct functioning.
The most common method for delivering test data from chip inputs to internal circuits under test (CUT), and observing their outputs, is called scan-design. In scan-design, registers or timing elements (e.g., flip-flops or latches) in the design are connected in one or more scan chains, which are used to gain access to internal nodes of the chip. Test patterns are shifted in via the scan chain(s), functional clock signals are pulsed to test the circuit during the “capture cycle(s)”, and the results are then shifted out to chip output pins and compared against the expected “good machine” results.
Straightforward application of scan techniques on a big digital IC can result in large vector sets with corresponding long tester time and memory requirements. The scan test compression techniques and circuits are commonly used in big digital ICs, such as CPU and SOC designs. Test compression techniques address this problem, by decompressing the scan inputs on chip and compressing the test outputs. For a fixed number of scan IOs in a given design, the scan chains in compression mode are much shorter in length than the scan chains without compression technique applied. The test data going through the short compression chains take a lot fewer clock cycles and therefore lot less times. This will reduce the chip test times significantly.
In addition to being useful for manufacturing “go/no go” testing, scan chains can also be used to “debug” chip designs. In this context, the chip is exercised in normal “functional mode” (for example, a computer or mobile-phone chip might execute assembly language instructions). At any time, the chip clock can be stopped, and the chip re-configured into “test mode”. At this point the internal state can be dumped out, or set to any desired values, by use of the scan chains. Another use of scan to aid debug includes scanning in an initial state to all memory elements and then going back to functional mode to perform system debug. One advantage of this is to bring the system to a known state without going through many clock cycles.